1. Field of the Invention
The present invention relates to a semiconductor device and method of fabricating the same. More particularly, it relates to a stacked gate flash memory device that can achieve high memory cell capacity.
2. Description of the Related Art
Complementary metal oxide semiconductor (CMOS) memory is generally categorized into two groups: random access memory (RAM) and read only memory (ROM). RAM is a volatile memory, wherein the stored data disappears when power is turned off. On the contrary, turning off power does not affect the stored data in a ROM.
In the past few years, market share of ROM has been continuously expanding, and the type attracting the most attention has been flash memory. The fact that a single memory cell is electrically programmable and multiple memory cell blocks are electrically erasable allows flexible and convenient application, superior to electrically programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM) and programmable read only memory (PROM). Furthermore, fabricating flash memory is cost effective. Having the above advantages, flash memory has been widely applied in consumer electronic products, such as digital cameras, digital video cameras, mobile phones, notebooks, personal stereos and personal digital assistant (PDA).
Since portability of these electrical consumer products is strongly prioritized by consumers, the size of the products must be minimal. As a result, capacity of flash memory must increase, and functions must be maximized while size thereof is continuously minimized. Having an increased amount of access data, capacity of memory cells has been enhanced from 4 to 256 MB, and even 1 G byte will become the market trend in the near future.
Hence, there is a need for a flash memory device with high memory cell capacity.
Accordingly, an object of the invention is to provide a stacked gate flash memory device that can achieve high integration of memory cells thereof.
Another object of the invention is to provide a method of fabricating a stacked gate flash memory device, wherein the driving currents in memory cells thereof can be increased without increasing the surfaces thereof.
Thus, a stacked gate flash memory cell in accordance with the present invention comprises a substrate having a cell trench and two adjacent isolation trenches therein, the cell trench having two substrate sides and two isolation sides contacting the adjacent isolation trenches, the isolation trench having two substrate sides and one cell side contacting the adjacent cell trench. A bottom insulating layer is disposed on the bottom of the cell trench. A pair of tunnel oxide layers, each is disposed on the substrate side of the cell trench and the bottom insulating layer. A pair of floating gates, each is disposed on the substrate side of the cell trench and covering the tunnel oxide layer. A conformal inter-gate dielectric layer overlies the tunnel oxide layers and the bottom insulating layer. A control gate overlies the inter-gate dielectric layer in the cell trench. Two pairs of source/drain regions, each is respectively disposed on the same substrate side of each isolation trench.
Furthermore, the method of fabricating the stacked gate flash memory cell in accordance with the present invention comprises providing a substrate, forming two parallel shallow trench isolation (STI) regions along a first direction thereon, forming a long trench in the substrate between the STI regions, wherein the long trench is parallel to the STI regions, forming a bottom insulating layer in the long trench, performing a threshold voltage (Vt) implant process on the sidewalls of the long trench, forming a tunnel oxide layer on each sidewall of the long trench, forming a floating gate on each sidewall of the long trench, covering the tunnel oxide layer thereon, forming a conformal inter-gate dielectric layer overlying the floating gates and the bottom insulating layer within the long trench, blanketly depositing a polysilicon layer covering the substrate and the inter-gate dielectric layer within the long trench, blanketly depositing a metal layer on the polysilicon layer, blanketly depositing a protecting layer on the metal layer, forming a plurality of parallel wordlines along a second direction, dividing the long trench into a plurality of first areas covered by the wordlines and a plurality of second areas not covered by the wordlines over the long trench, forming a spacer on each sidewall of the word lines, partially covering the second area, forming a plurality of third areas not covered by the wordlines and the spacers, forming a plurality of source/drain regions in the substrate adjacent to the second areas, and forming a second insulating layer within the second areas, wherein a plurality of cell trenches are formed under the first areas and a plurality of isolation trenches are formed under the second areas.
Advantages of the present invention are described herein.
First, cells of the flash memory device in accordance with the invention are disposed in trenches within a substrate that can achieve higher integration of memory cells than in the Prior Art.
Second, the channel between the source region and the drain region is horizontal. Source and drain regions can be formed on the same substrate side of the adjacent isolation trenches. Functions of source and drain regions can be decided according to the practical bitline design, providing suitable bitline design flexibility of the process.
Third, most of the fabricating processes in the invention are self-aligned such that additional lithography processes and number of masks for the whole fabricating process can be reduced.
A detailed description is given in the following embodiments with reference to the accompanying drawings.